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iris::x86::amd64 Namespace Reference

Namespaces

namespace  idt
 
namespace  page_structure
 
namespace  sd
 
namespace  ssd
 

Classes

struct  ApBootInfo
 
struct  ApicExtendedControlExtendId
 
struct  ApicExtendedControlInterruptEnable
 
struct  ApicExtendedControlSpecificEoi
 
struct  ApicExtendedFeatureExtendedId
 
struct  ApicExtendedFeatureExtendedLvtCount
 
struct  ApicExtendedFeatureInterruptEnable
 
struct  ApicExtendedFeatureSpecificEoi
 
struct  ApicExtendedRegisterPresent
 
struct  ApicInterruptCommandDeliveryMode
 
struct  ApicInterruptCommandDeliveryStatus
 
struct  ApicInterruptCommandDestination
 
struct  ApicInterruptCommandDestinationMode
 
struct  ApicInterruptCommandDestinationShorthand
 
struct  ApicInterruptCommandLevel
 
struct  ApicInterruptCommandRemoteReadStatus
 
struct  ApicInterruptCommandTriggerMode
 
struct  ApicInterruptCommandVector
 
struct  ApicLvtEntryDeliveryStatus
 
struct  ApicLvtEntryMask
 
struct  ApicLvtEntryMessageType
 
struct  ApicLvtEntryRemoteIrr
 
struct  ApicLvtEntryTimerMode
 
struct  ApicLvtEntryTriggerMode
 
struct  ApicLvtEntryVector
 
struct  ApicMaxLvtEntry
 
struct  ApicVersion
 
struct  GDTR
 
struct  IDTR
 
class  IoApic
 
struct  IoApicMaxRedirectionEntry
 
struct  IoApicRedirectionTableEntryDeliveryMode
 
struct  IoApicRedirectionTableEntryDeliveryStatus
 
struct  IoApicRedirectionTableEntryDestination
 
struct  IoApicRedirectionTableEntryDestinationMode
 
struct  IoApicRedirectionTableEntryMask
 
struct  IoApicRedirectionTableEntryPolarity
 
struct  IoApicRedirectionTableEntryRemoteIrr
 
struct  IoApicRedirectionTableEntryTriggerMode
 
struct  IoApicRedirectionTableEntryVector
 IO APIC Redirection Table Entry. More...
 
struct  IoApicVersion
 IO APIC Version Register. More...
 
class  LocalApic
 
class  LocalApicTimer
 
class  Pic
 
class  PitTimer
 
struct  TSS
 

Typedefs

using IoApicVersionRegister = di::BitStruct<4, IoApicVersion, IoApicMaxRedirectionEntry>
 
using IoApicRedirectionTableEntry
 
using ApicVersionRegister = di::BitStruct<4, ApicVersion, ApicMaxLvtEntry, ApicExtendedRegisterPresent>
 Local APIC Version Register.
 
using ApicExtendedFeatureRegister
 Local APIC Extended Feature Register.
 
using ApicExtendedControlRegister
 Local APIC Extended Control Register.
 
using ApicLvtEntry
 Local APIC LVT Entry.
 
using ApicInterruptCommandRegister
 Local APIC Interrupt Command Register.
 

Enumerations

enum class  IoApicAccessOffset : u8 { RegisterSelect = 0x00 , Window = 0x10 }
 IO APIC Access Register Offsets. More...
 
enum class  IoApicOffset : u8 { Id = 0x00 , Version = 0x01 , ArbitrationId = 0x02 , RedirectionTable = 0x10 }
 IO APIC Register Offsets. More...
 
enum class  IoApicDestinationMode { Physical = 0 , Logical = 1 }
 IO APIC Destination Mode. More...
 
enum class  ApicOffset : u16 {
  Id = 0x0020 , Version = 0x0030 , TaskPriority = 0x0080 , ArbitrationPriority = 0x0090 ,
  ProcessorPriority = 0x00A0 , EndOfInterrupt = 0x00B0 , RemoteRead = 0x00C0 , LogicalDestination = 0x00D0 ,
  DestinationFormat = 0x00E0 , SpuriousInterruptVector = 0x00F0 , InService = 0x0100 , TriggerMode = 0x0180 ,
  InterruptRequest = 0x0200 , ErrorStatus = 0x0280 , LvtTimer = 0x0320 , InterruptCommandLow = 0x0300 ,
  InterruptCommandHigh = 0x0310 , TimerLvtEntry = 0x320 , ThermalLvtEntry = 0x0330 , PerformanceLvtEntry = 0x0340 ,
  Lint0Entry = 0x0350 , Lint1Entry = 0x0360 , ErrorEntry = 0x0370 , TimerInitialCount = 0x0380 ,
  TimerCurrentCount = 0x0390 , TimerDivideConfiguration = 0x03E0 , ExtendedFeature = 0x0400 , ExtendedControl = 0x0410 ,
  SpecificEndOfInterrupt = 0x0420 , InterruptEnable = 0x0480 , ExtendedLvtEntries = 0x0500
}
 Local APIC Register Offsets. More...
 
enum class  ApicMessageType : u8 {
  Fixed = 0b000 , LowestPriority = 0b001 , Smi = 0b010 , RemoteRead = 0b011 ,
  Nmi = 0b100 , Init = 0b101 , Startup = 0b110 , External = 0b111
}
 Local APIC Message Type. More...
 
enum class  ApicTimerDivideConfiguration : u32 {
  DivideBy2 = 0b0000 , DivideBy4 = 0b0001 , DivideBy8 = 0b0010 , DivideBy16 = 0b0011 ,
  DivideBy32 = 0b1000 , DivideBy64 = 0b1001 , DivideBy128 = 0b1010 , DivideBy1 = 0b1011
}
 Local APIC Timer Divide Configuration. More...
 
enum class  ApicDestinationShorthand { None = 0b00 , Self = 0b01 , AllIncludingSelf = 0b10 , AllExcludingSelf = 0b11 }
 Local APIC Destination Shorthands. More...
 
enum class  ModelSpecificRegister : u32 {
  LocalApicBase = 0x1BU , Star = 0xC0000081U , LStar = 0xC0000082U , CStar = 0xC0000083U ,
  SfMask = 0xC0000084U , FsBase = 0xC0000100U , GsBase = 0xC0000101U , KernelGsBase = 0xC0000102U
}
 

Functions

void init_gdt ()
 
void tag_invoke (di::Tag< send_eoi >, IoApic &, IrqLine irq_line)
 
void tag_invoke (di::Tag< disable_irq_line >, IoApic &self, IrqLine irq_line)
 
void tag_invoke (di::Tag< enable_irq_line >, IoApic &self, IrqLine irq_line)
 
auto tag_invoke (di::Tag< responsible_irq_line_range >, IoApic const &self) -> IrqLineRange
 
void init_io_apic ()
 
void init_local_apic (bool print_info)
 
 asm (".code16\n" ".set __iris_ap_phys_start, 0x8000\n" ".global __iris_ap_entry_start\n" "__iris_ap_entry_start:\n" "cli\n" "mov %cr4, %eax\n" "or $(1 << 5 | 1 << 7), %eax\n" "mov %eax, %cr4\n" "mov $0xC0000080, %ecx\n" "rdmsr\n" "or $(1 << 8 | 1 << 11), %eax\n" "wrmsr\n" "mov (__iris_ap_cr3 - __iris_ap_entry_start + __iris_ap_phys_start), %eax\n" "mov %eax, %cr3\n" "mov %cr0, %eax\n" "or $(1 << 31 | 1 << 0), %eax\n" "mov %eax, %cr0\n" "lgdtl (__iris_ap_gdtr - __iris_ap_entry_start + __iris_ap_phys_start)\n" "mov $6, %ebx\n" "ljmp $0x28, $(__iris_ap_entry64 - __iris_ap_entry_start + __iris_ap_phys_start)\n" ".code64\n" "__iris_ap_entry64:\n" "xor %rax, %rax\n" "mov %ax, %ds\n" "mov %ax, %es\n" "mov %ax, %fs\n" "mov %ax, %gs\n" "mov %ax, %ss\n" "mov (__iris_ap_stack_pointer - __iris_ap_entry_start + __iris_ap_phys_start), %rsp\n" "mov $(__iris_ap_boot_info - __iris_ap_entry_start + __iris_ap_phys_start), %rdi\n" "mov $iris_ap_entry, %rax\n" "call *%rax\n" "__iris_ap_loop:\n" "hlt\n" "jmp __iris_ap_loop\n" ".align 16\n" "__iris_ap_boot_info:\n" "__iris_ap_cr3:\n" ".skip 8\n" "__iris_ap_stack_pointer:\n" ".skip 8\n" "__iris_ap_processor:\n" ".skip 8\n" "__iris_ap_gdtr:\n" ".skip 16\n" "__iris_ap_gdt:\n" ".skip 88\n" "__iris_ap_entry_end:\n")
 
void __iris_ap_entry_start ()
 
void __iris_ap_boot_info ()
 
void __iris_ap_gdt ()
 
void __iris_ap_entry_end ()
 
void iris_ap_entry (ApBootInfo *info_in)
 
void init_alternative_processors ()
 
void init_pic ()
 
void init_pit ()
 
void init_sb16 ()
 
auto sb16_write_audio (UserspaceBuffer< byte const > data) -> Expected< usize >
 
void init_serial_early_boot ()
 
void init_serial ()
 
void init_tss ()
 

Variables

constexpr auto dsp_read_port = 0x22A_u16
 
constexpr auto dsp_write_port = 0x22C_u16
 
constexpr auto dsp_status_port = 0x22E_u16
 
constexpr auto dsp_ack_port = 0x22F_u16
 
constexpr auto dma_max_page_count = 8_u32
 

Typedef Documentation

◆ ApicExtendedControlRegister

using iris::x86::amd64::ApicExtendedControlRegister
Initial value:
di::BitStruct<4, ApicExtendedControlInterruptEnable, ApicExtendedControlSpecificEoi, ApicExtendedControlExtendId>
di::bit::BitStruct
Definition bit_struct.h:11

Local APIC Extended Control Register.

See AMD64 Programmer's Manual; Volume 2; Section 16.3.6 Figure 16-6.

◆ ApicExtendedFeatureRegister

using iris::x86::amd64::ApicExtendedFeatureRegister
Initial value:
di::BitStruct<4, ApicExtendedFeatureInterruptEnable, ApicExtendedFeatureSpecificEoi,
ApicExtendedFeatureExtendedId, ApicExtendedFeatureExtendedLvtCount>

Local APIC Extended Feature Register.

See AMD64 Programmer's Manual; Volume 2; Section 16.3.5 Figure 16-5.

◆ ApicInterruptCommandRegister

using iris::x86::amd64::ApicInterruptCommandRegister
Initial value:
di::BitStruct<8, ApicInterruptCommandVector, ApicInterruptCommandDeliveryMode, ApicInterruptCommandDestinationMode,
ApicInterruptCommandDeliveryStatus, ApicInterruptCommandLevel, ApicInterruptCommandTriggerMode,
ApicInterruptCommandRemoteReadStatus, ApicInterruptCommandDestinationShorthand,
ApicInterruptCommandDestination>

Local APIC Interrupt Command Register.

See AMD64 Programmer's Manual; Volume 2; Section 16.5 Figure 16-18.

◆ ApicLvtEntry

using iris::x86::amd64::ApicLvtEntry
Initial value:
di::BitStruct<4, ApicLvtEntryVector, ApicLvtEntryMessageType, ApicLvtEntryDeliveryStatus, ApicLvtEntryRemoteIrr,
ApicLvtEntryTriggerMode, ApicLvtEntryMask, ApicLvtEntryTimerMode>
iris::x86::amd64::ApicLvtEntryMask
Definition local_apic.h:97
iris::x86::amd64::ApicLvtEntryRemoteIrr
Definition local_apic.h:95
iris::x86::amd64::ApicLvtEntryTimerMode
Definition local_apic.h:98
iris::x86::amd64::ApicLvtEntryVector
Definition local_apic.h:92

Local APIC LVT Entry.

See [OSDEV](Local_Vector_Table_Registers) and AMD64 Programmer's Manual; Volume 2; Section 16.4 Figure 16-7.

◆ ApicVersionRegister

using iris::x86::amd64::ApicVersionRegister = di::BitStruct<4, ApicVersion, ApicMaxLvtEntry, ApicExtendedRegisterPresent>

Local APIC Version Register.

See AMD64 Programmer's Manual; Volume 2; Section 16.3.4 Figure 16-4.

◆ IoApicRedirectionTableEntry

using iris::x86::amd64::IoApicRedirectionTableEntry
Initial value:
di::BitStruct<8, IoApicRedirectionTableEntryVector, IoApicRedirectionTableEntryDeliveryMode,
IoApicRedirectionTableEntryDestinationMode, IoApicRedirectionTableEntryDeliveryStatus,
IoApicRedirectionTableEntryPolarity, IoApicRedirectionTableEntryRemoteIrr,
IoApicRedirectionTableEntryTriggerMode, IoApicRedirectionTableEntryMask,
IoApicRedirectionTableEntryDestination>
iris::x86::amd64::IoApicRedirectionTableEntryVector
IO APIC Redirection Table Entry.
Definition io_apic.h:54

◆ IoApicVersionRegister

using iris::x86::amd64::IoApicVersionRegister = di::BitStruct<4, IoApicVersion, IoApicMaxRedirectionEntry>

Enumeration Type Documentation

◆ ApicDestinationShorthand

enum class iris::x86::amd64::ApicDestinationShorthand
strong

Local APIC Destination Shorthands.

See AMD64 Programmer's Manual; Volume 2; Section 16.5.

Enumerator
None 
Self 
AllIncludingSelf 
AllExcludingSelf 

◆ ApicMessageType

enum class iris::x86::amd64::ApicMessageType : u8
strong

Local APIC Message Type.

Warning
Only Fixed, Smi, Nmi, and External are valid for LVT entries. All types are valid when sending IPIs.

See AMD64 Programmer's Manual; Volume 2; Section 16.5.

Enumerator
Fixed 
LowestPriority 
Smi 
RemoteRead 
Nmi 
Init 
Startup 
External 

◆ ApicOffset

enum class iris::x86::amd64::ApicOffset : u16
strong

Local APIC Register Offsets.

See OSDEV or AMD64 Programmer's Manual; Volume 2; Section 16.3.2 Figure 16-2.

Enumerator
Id 
Version 
TaskPriority 
ArbitrationPriority 
ProcessorPriority 
EndOfInterrupt 
RemoteRead 
LogicalDestination 
DestinationFormat 
SpuriousInterruptVector 
InService 
TriggerMode 
InterruptRequest 
ErrorStatus 
LvtTimer 
InterruptCommandLow 
InterruptCommandHigh 
TimerLvtEntry 
ThermalLvtEntry 
PerformanceLvtEntry 
Lint0Entry 
Lint1Entry 
ErrorEntry 
TimerInitialCount 
TimerCurrentCount 
TimerDivideConfiguration 
ExtendedFeature 
ExtendedControl 
SpecificEndOfInterrupt 
InterruptEnable 
ExtendedLvtEntries 

◆ ApicTimerDivideConfiguration

enum class iris::x86::amd64::ApicTimerDivideConfiguration : u32
strong

Local APIC Timer Divide Configuration.

See AMD64 Programmer's Manual; Volume 2; Section 16.4.1 Figure 16-11.

Enumerator
DivideBy2 
DivideBy4 
DivideBy8 
DivideBy16 
DivideBy32 
DivideBy64 
DivideBy128 
DivideBy1 

◆ IoApicAccessOffset

enum class iris::x86::amd64::IoApicAccessOffset : u8
strong

IO APIC Access Register Offsets.

See Intel's 82093AA IOAPIC Specification; Section 3.0. Table 1.

Enumerator
RegisterSelect 
Window 

◆ IoApicDestinationMode

enum class iris::x86::amd64::IoApicDestinationMode
strong

IO APIC Destination Mode.

See Intel's 82093AA IOAPIC Specification; Section 3.2.4.

Enumerator
Physical 

Send to a single processor.

Logical 

Send to a bit mask of processors.

◆ IoApicOffset

enum class iris::x86::amd64::IoApicOffset : u8
strong

IO APIC Register Offsets.

See Intel's 82093AA IOAPIC Specification; Section 3.0. Table 2.

Enumerator
Id 
Version 
ArbitrationId 
RedirectionTable 

◆ ModelSpecificRegister

enum class iris::x86::amd64::ModelSpecificRegister : u32
strong
Enumerator
LocalApicBase 
Star 
LStar 
CStar 
SfMask 
FsBase 
GsBase 
KernelGsBase 

Function Documentation

◆ __iris_ap_boot_info()

void iris::x86::amd64::__iris_ap_boot_info ( )
extern

◆ __iris_ap_entry_end()

void iris::x86::amd64::__iris_ap_entry_end ( )
extern

◆ __iris_ap_entry_start()

void iris::x86::amd64::__iris_ap_entry_start ( )
extern

◆ __iris_ap_gdt()

void iris::x86::amd64::__iris_ap_gdt ( )
extern

◆ asm()

iris::x86::amd64::asm ( ".code16\n" ".set __iris_ap_phys_start,
0x8000\n" ".global __iris_ap_entry_start\n" "__iris_ap_entry_start:\n" "cli\n" "mov % cr4,
%eax\n" "or $1<< 5|1<< 7,
%eax\n" "mov % eax,
%cr4\n" "mov $0xC0000080,
%ecx\n" "rdmsr\n" "or $1<< 8|1<< 11,
%eax\n" "wrmsr\n" " mov__iris_ap_cr3 - __iris_ap_entry_start+__iris_ap_phys_start,
%eax\n" "mov % eax,
%cr3\n" "mov % cr0,
%eax\n" "or $1<< 31|1<< 0,
%eax\n" "mov % eax,
%cr0\n" "lgdtl(__iris_ap_gdtr - __iris_ap_entry_start+__iris_ap_phys_start)\n" "mov $6,
%ebx\n" "ljmp $0x28,
$(__iris_ap_entry64 - __iris_ap_entry_start+__iris_ap_phys_start)\n" ".code64\n" "__iris_ap_entry64:\n" "xor %,
%rax\n" "mov % ax,
%ds\n" "mov % ax,
%es\n" "mov % ax,
%fs\n" "mov % ax,
%gs\n" "mov % ax,
%ss\n" " mov__iris_ap_stack_pointer - __iris_ap_entry_start+__iris_ap_phys_start,
%rsp\n" "mov $__iris_ap_boot_info - __iris_ap_entry_start+__iris_ap_phys_start,
%rdi\n" "mov $iris_ap_entry,
%rax\n" "call *%rax\n" "__iris_ap_loop:\n" "hlt\n" "jmp __iris_ap_loop\n" ".align 16\n" "__iris_ap_boot_info:\n" "__iris_ap_cr3:\n" ".skip 8\n" "__iris_ap_stack_pointer:\n" ".skip 8\n" "__iris_ap_processor:\n" ".skip 8\n" "__iris_ap_gdtr:\n" ".skip 16\n" "__iris_ap_gdt:\n" ".skip 88\n" "__iris_ap_entry_end:\n"  )

◆ init_alternative_processors()

void iris::x86::amd64::init_alternative_processors ( )

◆ init_gdt()

void iris::x86::amd64::init_gdt ( )

◆ init_io_apic()

void iris::x86::amd64::init_io_apic ( )

◆ init_local_apic()

void iris::x86::amd64::init_local_apic ( bool print_info)

◆ init_pic()

void iris::x86::amd64::init_pic ( )

◆ init_pit()

void iris::x86::amd64::init_pit ( )

◆ init_sb16()

void iris::x86::amd64::init_sb16 ( )

◆ init_serial()

void iris::x86::amd64::init_serial ( )

◆ init_serial_early_boot()

void iris::x86::amd64::init_serial_early_boot ( )

◆ init_tss()

void iris::x86::amd64::init_tss ( )

◆ iris_ap_entry()

void iris::x86::amd64::iris_ap_entry ( ApBootInfo * info_in)

◆ sb16_write_audio()

auto iris::x86::amd64::sb16_write_audio ( UserspaceBuffer< byte const > data) -> Expected< usize >

◆ tag_invoke() [1/4]

void iris::x86::amd64::tag_invoke ( di::Tag< disable_irq_line > ,
IoApic & self,
IrqLine irq_line )

◆ tag_invoke() [2/4]

void iris::x86::amd64::tag_invoke ( di::Tag< enable_irq_line > ,
IoApic & self,
IrqLine irq_line )

◆ tag_invoke() [3/4]

auto iris::x86::amd64::tag_invoke ( di::Tag< responsible_irq_line_range > ,
IoApic const & self ) -> IrqLineRange

◆ tag_invoke() [4/4]

void iris::x86::amd64::tag_invoke ( di::Tag< send_eoi > ,
IoApic & ,
IrqLine irq_line )

Variable Documentation

◆ dma_max_page_count

auto iris::x86::amd64::dma_max_page_count = 8_u32
constexpr

◆ dsp_ack_port

auto iris::x86::amd64::dsp_ack_port = 0x22F_u16
constexpr

◆ dsp_read_port

auto iris::x86::amd64::dsp_read_port = 0x22A_u16
constexpr

◆ dsp_status_port

auto iris::x86::amd64::dsp_status_port = 0x22E_u16
constexpr

◆ dsp_write_port

auto iris::x86::amd64::dsp_write_port = 0x22C_u16
constexpr